REMINDER: Accellera Systems Initiative Announces Call for Nominations for 2012 Technical Excellence Award for EDA and IP Standards Contributions
Nominations Are Due January 27, 2012; Recipient Will Be Recognized at Organization's DVCon on February 27, 2012
(firmenpresse) - SAN JOSE, CA -- (Marketwire) -- 01/25/12 --
, formed last year from the merger of Accellera and the Open SystemC Initiative (OSCI), two industry organizations focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, will announce the recipient of its first annual at its annual Design and Verification Conference () on February 27, 2012 at the Doubletree hotel in San Jose, California. The Award recognizes the outstanding achievements of a Technical Subcommittee member. Candidates can be nominated by the industry at large and are endorsed and selected by participants in Accellera Systems Initiative Committees. Award nominations are due January 27, 2012. To nominate an individual, please visit .
DVCon
February 27-March 1, 2012
DoubleTree Hotel, San Jose, CA
Accellera Systems Initiative Technical Subcommittees produce effective and efficient EDA and IP standards for today's advanced IC designs. Participants include member companies and industry contributors. Technical contributors typically have many years of practical experience with IC design and developing and using EDA tools.
Accellera Systems Initiative Technical Committees include:
Analog/Mixed-Signal extensions to Verilog (Verilog-AMS)
Analog/Mixed-Signal extensions to SystemC™
Configuration, Control and Inspection (CCI) standards for exchanging information between SystemC models and tools
IP Tagging for data-driven tracking of soft IP
IP-XACT™ metadata standard for IP integration
Open Verification Library (OVL) assertion library
Standard for Co-Emulation Modeling Interface (SCE-MI)
Synthesizable subset of SystemC
SystemC language standard
SystemC Verification (SCV) library
Transaction Level Modeling (TLM) standards for modeling systems based on memory-mapped busses in SystemC
Unified Coverage Interoperability Standard (UCIS) for verification coverage interoperability
Universal Verification Methodology (UVM™) standard
is an independent, not-for profit organization, dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit . For membership information, please email .
is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by , an organization focused on the creation and adoption of EDA and IP standards. For more information, please visit .
For more information about DVCon, please visit . Follow (at)dvcon on Twitter or to comment, please use #dvcon.
UVM, IP-XACT, SystemC, OSCI, and Open SystemC Initiative are trademarks of Accellera Systems Initiative Inc.
All other trademarks and tradenames are the property of their respective owners.
Press Contact
Georgia Marszalek
ValleyPR LLC for Accellera Systems Initiative
+1 650-345-7477
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Datum: 25.01.2012 - 11:00 Uhr
Sprache: Deutsch
News-ID 107498
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Electronics & Communications
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