Verific Design Automation Selected to Support Blue Pearl Software Suite
SystemVerilog, VHDL Parsers, RTL Elaborator Integrated With Leading-Edge FPGA and ASIC Electronic Design Software
(firmenpresse) - ALAMEDA, CA -- (Marketwire) -- 02/16/12 -- Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL front-end solutions, has been selected by Blue Pearl Software to support its Blue Pearl Software Suite.
The Blue Pearl Software Suite is register transfer level (RTL) analysis software used by field programmable gate array (FPGA) and application specific integrated circuit (ASIC) designers. Verific's SystemVerilog and VHDL parsers and RTL elaborator have been integrated with Blue Pearl's leading-edge software used for comprehensive RTL analysis, clock-domain crossing checks (CDCs) and automatic Synopsys Design Constraints (SDC) constraint generation. This announcement corresponds to Blue Pearl Software's introduction today of version 6.0 of its software suite.
"It was logical to us to choose Verific Design Automation for the 6.0 version of the Blue Pearl Software Suite since Verific is an instantly recognizable brand-name provider of Verilog, SystemVerilog and VHDL parsers," remarks Scott Aron Bloom, Blue Pearl's director of product development. "Design teams applauded us when we selected Verific as the front-end for our Blue Pearl Software Suite."
"Blue Pearl Software wisely determined that building and supporting in-house parsers for Verilog, SystemVerilog and VHDL is simply not cost-effective and can be counterproductive," affirms Michiel Ligthart, Verific's chief operating officer. "Blue Pearl's differentiator is its ability to create and verify timing constraints and that is what its development team is focusing on. This is a sound decision and the correct one for Blue Pearl customers."
The Blue Pearl Software Suite automates design analysis, CDC checking and Synopsys Design Constraints (SDC) creation, visualization and validation, giving users immediate feedback through powerful visualization techniques for validating automatically generated timing constraints.
Since its founding in 1999, Verific's software has served as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Additionally, Verific recently announced availability of its UPF parser, now part of the Verific Parser Platform. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.
Blue Pearl Software, Inc. provides next-generation electronic design automation (EDA) software that uses new and innovative technology to reduce design flow iterations and increase designer productivity early in the digital design flow. The Blue Pearl Software Suite checks register transfer level (RTL) designs for functional errors and automatically generates comprehensive and accurate Synopsys Design Constraints (SDC) that improve quality of results (QoR) and reduce FPGA and ASIC design risks.
Visit Blue Pearl Software at .
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: . Website: .
Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822
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Datum: 16.02.2012 - 16:30 Uhr
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News-ID 115694
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