Docea Ships New Version of Power and Thermal Analysis Software, Announces Enhanced Thermal Modeler, Schedules Demos at DAC
Tools Address Power and Thermal Coupling at Architectural Level, Architecture Validation, Track Power Budgets
(firmenpresse) - SAN FRANCISCO, CA -- (Marketwire) -- 05/22/12 -- (DAC) - May 22, 2012 - , the design-for-low-power company that delivers Electronic System Level (ESL) software tools for power and thermal analysis and modelling, announced that it is shipping ™ 3.0 with an event scheduler for enhanced scenario creation capabilities and support for thermal models generated by its AceThermalModeler for coupled power and thermal simulations capabilities. In addition, it is announcing 1.1 with an enhanced 3D viewer for fast model debugging.
models and optimizes electronic design power and thermal consumption for early architecture exploration, architecture validation and power budget tracking during electronic design implementation stages, and creates compact RC thermal models for complete systems from system on chips (SoCs) to System-in-Packages (SiP), 3D ICs to complete boards. These compact thermal models are used for fast steady state or dynamic thermal responses enabling early system floorplan exploration or partitioning, improved system packaging and integration architectures, and early exploration of power and thermal management policies to reduce temperature peaks and manage temperature gradients across the system.
Aceplorer 3.0's new features include an event scheduler to automate the creation of timed scenarios from parallel tasks and workload definitions with different arbitration schemes, along with the support for thermal models created with AceThermalModeler. The event scheduler complements the existing timed flow chart creation and vcd import capabilities already in place and used to automate the creations of use cases.
AceThermalModeler 1.1 will be demonstrated for the first time at DAC. Its new features include an enhanced graphical user interface (GUI) with capabilities for 3D and thermal model creation and debugging. The Docea team will demonstrate how to use its thermal models to validate thermal management policies, simulate power-thermal coupling, detect thermal runaway risks, and improve the productivity of thermal experts and the architecture team.
Monday-Wednesday, June 4-6, 2012 9 am to 6 pm
Docea Booth #1702
Moscone Convention Center, San Francisco, California
To request a private demo, please register
To schedule a meeting with Docea Power, please email Ridha.Hamza (a)doceapower.com or call +33 (0)4 27 85 82 97
For more information about Docea, please visit .
To register for , please visit .
develops and commercializes a new generation of methodology and tools for enabling faster and more reliable power and thermal modelling at the electronic systems level (ESL). Docea solutions offer a consistent approach for architectural exploration and optimizing power and thermal behaviour of electronic systems, at an early stage of an electronic design project.
Docea's customers include manufacturers of electronic systems, chips and boards that target wireless, multimedia, consumer, networking and automotive applications. The company has offices near Grenoble, France, and in San Jose, California, USA, and sales offices in Japan and Korea.
For more information: .
Notes to editors:
Graphics are available on request.
Acronyms and Definition
ESL: Electronic System Level
SiP: System-in-Package
RC: R stands for Resistor and C for Capacitor
SoC: System-on-Chip
Vcd: value change dump; vcd is a standard trace format in the electronic design industry.
Aceplorer and AceThermalModeler are trademarks of Docea Power.
All other trademarks or tradenames are the properties of their respective owners.
Europe:
Chantal Cochini
l'Ops PR
+33(0)1 42 71 30 93
US:
Georgia Marszalek
ValleyPR LLC
+1 (650) 345-7477
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Datum: 22.05.2012 - 15:42 Uhr
Sprache: Deutsch
News-ID 149009
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