Verific Design Automation's Industry-Standard SystemVerilog, VHDL Parsers Linked With Aldec's Hardware Emulation Solution
Companies Sign Licensing Agreement
(firmenpresse) - ALAMEDA, CA -- (Marketwire) -- 08/15/12 -- Verific Design Automation today announced it licensed its industry-standard, IEEE-compliant SystemVerilog and VHDL platform to Aldec, Inc., a global leader in electronic design verification, to be included into its Hardware Emulation Solution (HES™).
HES is a unified platform for bit-level simulation acceleration, transaction-level emulation, system architecture exploration, hardware/software co-verification, virtual modeling and prototyping. Verific's SystemVerilog and VHDL parsers and register transfer level (RTL) elaborators have been integrated with its Design Verification Manager (DVM™) software.
"Full language support (including SystemVerilog), well-tested software and outstanding customer support made integration with the Verific compiler an easy choice to simplify the design setup flow for HES-DVM," says Zibi Zalewski, general manager of Aldec's Hardware Division. "We value the relationship we have established with Verific. With their compiler, HES-DVM now offers new debugging instrumentation and SCE-MI2.0 DPI Function Based support, and with their flexible customer support, our team was able to speed up the development schedule without any major issues."
"Aldec is an impressive company and one that we're proud to be working with," comments Michiel Ligthart, Verific's president and chief operating officer. "Emulation is a complex engineering problem that Aldec and HES have mastered."
Verific's software has been the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs since the company was founded in 1999. The Verific Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF. A recent addition to its product offerings is a Verific Perl module, an interface to its SystemVerilog and VHDL parsers and elaborators. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.
Aldec, Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. More information about the company and its products is available at .
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: . Website: .
Aldec and HEC-DVM are trademarks of Aldec, Inc. Aldec and Verific Design Automation acknowledge trademarks or registered trademarks of other organizations for their respective products and services.
For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822
Christina Toole
Marketing Manager for Aldec, Inc.
(702) 990-4400
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Datum: 15.08.2012 - 15:00 Uhr
Sprache: Deutsch
News-ID 174981
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