REMINDER: At EDSFair, Blue Pearl Demos FPGA Design Tools for RTL Signoff, Presents on Overcoming Timing Challenges

(firmenpresse) - YOKOHAMA, JAPAN -- (Marketwire) -- 11/11/12 --
, the provider of EDA software that accelerates RTL signoff for FPGA designs
Demonstrations of the of the at and a presentation on Overcoming the Timing Challenges of Advanced FPGA Designs
Presentation
11:00 to 11:45, November 15
EG-1
Demonstrations
November 15 and 16
Booth D-45
Pacifico
Yokohama, Japan
To schedule an evaluation, meeting or demo, .
For more information, please visit the Blue Pearl .
For more information about EDSFair, please visit
For information, on Blue Pearl's longest path analysis, please to read our article .
For information on how Blue Pearl enables SoC RTL analysis, to read our white paper, .
The works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs drive the efficiency of the synthesis and place and route phases of FPGA design implementation, and reduce iterations and overall design time. Its Visual Verification Environment™ makes it easy to use.
The company's collaboration with Synopsys offers an optimized flow that works with Synopsys' Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can automatically generate an exhaustive set of constraints that address false and multi-cycle paths that are compatible with Synopsys' synthesis flow.
Blue Pearl Software, Inc. is a member of the , and provides EDA software that accelerates RTL signoff for FPGA designs. The checks RTL designs for functional errors and automatically generates comprehensive and accurate Synopsys Design Constraints (SDCs) to improve Quality of Results (QoR) and reduce design risks.
Visit Blue Pearl Software at .
Acronyms
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FPGA: Field Programmable Gate Array
QoR: Quality of Results
RTL: Register Transfer Level
SDC: Synopsys Design Constraints
SoC: System-on-Chip
Visual Verification Environment is a trademark of Blue Pearl Software, Inc.
All other trademarks are property of their respective owners.
Press Contact:
Georgia Marszalek
ValleyPR LLC for Blue Pearl Software
+1-650.345.7477
Themen in dieser Pressemitteilung:
Unternehmensinformation / Kurzprofil:
Bereitgestellt von Benutzer: MARKETWIRE
Datum: 11.11.2012 - 22:00 Uhr
Sprache: Deutsch
News-ID 201900
Anzahl Zeichen: 0
contact information:
Town:
YOKOHAMA, JAPAN
Kategorie:
Electronics & Communications
Diese Pressemitteilung wurde bisher 328 mal aufgerufen.
Die Pressemitteilung mit dem Titel:
"REMINDER: At EDSFair, Blue Pearl Demos FPGA Design Tools for RTL Signoff, Presents on Overcoming Timing Challenges"
steht unter der journalistisch-redaktionellen Verantwortung von
Blue Pearl Software (Nachricht senden)
Beachten Sie bitte die weiteren Informationen zum Haftungsauschluß (gemäß TMG - TeleMedianGesetz) und dem Datenschutz (gemäß der DSGVO).