eSilicon Optimizes IP for Cost-Effective 2.5D Integration
eSilicon's Lisa Minwell Will Discuss Technologies and Techniques for Optimizing 2.5D Designs for Power and Cost Effectiveness at MEPTEC
(firmenpresse) - SAN JOSE, CA -- (Marketwired) -- 01/08/15 --
Lisa Minwell, senior director of marketing for the IP Solutions Group
Keynote presentationOptimizing IP for Cost-effective 2.5D Integration
: MEPTEC luncheon, Biltmore Hotel, Santa Clara
Wednesday, January 14, 2015
Registration: 11:30am
Presentation: 12:00-1:15pm
:
Heterogeneous integration on silicon interposers provides a viable solution to the demand in the computer and consumer electronics markets for higher processing speed, lower power and increased functionalities. Lisa Minwell of eSilicon will discuss technologies and techniques for optimizing 2.5D designs for power and cost effectiveness.
As senior director of marketing, IP Solutions Group, eSilicon Corporation, Lisa Minwell is responsible for the company's physical IP product portfolio. Before joining eSilicon, Lisa was product marketing manager for memory products at Synopsys, Inc. and director of product marketing for Virage Logic's memory products. She held various design and managerial positions with Motorola, Inc., where her experience included memory compiler development, SRAM design engineering, CAD and IT management and research and development of DRAM and EEPROMs. Lisa holds a Bachelor of Science in Microelectronic Engineering from the Rochester Institute of Technology, Rochester, New York.
eSilicon, a leading independent semiconductor design and manufacturing solutions provider, delivers custom ICs and custom IP to OEMs, independent device manufacturers (IDMs), fabless semiconductor companies (FSCs) and wafer foundries through a fast, flexible, lower-risk, automated path to volume production. eSilicon serves a wide variety of markets including communications, computer, consumer, industrial products and medical.
eSilicon -- Enabling Your Silicon Success™
eSilicon is a registered trademark, and the eSilicon logo and Enabling Your Silicon Success are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.
Contacts:
Sally Slemons
eSilicon Corporation
408.635.6409
Susan Cain
Cain Communications
408.393.4794
Themen in dieser Pressemitteilung:
Unternehmensinformation / Kurzprofil:
Datum: 08.01.2015 - 13:30 Uhr
Sprache: Deutsch
News-ID 363132
Anzahl Zeichen: 0
contact information:
Town:
SAN JOSE, CA
Kategorie:
Electronic Design Architecture
Diese Pressemitteilung wurde bisher 292 mal aufgerufen.
Die Pressemitteilung mit dem Titel:
"eSilicon Optimizes IP for Cost-Effective 2.5D Integration"
steht unter der journalistisch-redaktionellen Verantwortung von
eSilicon (Nachricht senden)
Beachten Sie bitte die weiteren Informationen zum Haftungsauschluß (gemäß TMG - TeleMedianGesetz) und dem Datenschutz (gemäß der DSGVO).
