System-Level Advantages of 3D Integration
eSilicon's Mike Gianfagna to Participate in Panel Discussion on 3D Integration at the International Wafer-Level Packaging Conference (IWLPC)
(firmenpresse) - SAN JOSE, CA -- (Marketwired) -- 11/04/14 --
Mike Gianfagna, vice president of marketing at , a leading independent semiconductor design and manufacturing solutions provider
Panel discussion: System Level Advantages of 3D Integration
:
International Wafer-Level Packaging Conference (IWLPC) 2014, DoubleTree San Jose, Oak Ballroom
November 11, 2014, 1:15-2:45pm
Panelists include Mike Gianfagna, eSilicon; Ramakanth Alapati, GLOBALFOUNDRIES; Bel Haba, Google; Simon McElrea, Invensas Corporation; E. Jan Vardaman, TechSearch International Inc.; Robert Patti, Tezzaron Semiconductor Corp. and Rozalia Beica, Yole Développement. Moderated by Francoise von Trapp, 3D InCites, Inc.
System-level integrators and manufacturers will face off in a discussion about the system-level advantages of 3D IC, whether 3D ICs can solve the issues of SoC design complexity and the cost of CMOS scaling to future nodes
eSilicon, a leading independent semiconductor design and manufacturing solutions provider, delivers custom ICs and custom IP to OEMs, independent device manufacturers (IDMs), fabless semiconductor companies (FSCs) and wafer foundries through a fast, flexible, lower-risk, automated path to volume production. eSilicon serves a wide variety of markets including communications, computer, consumer, industrial products and medical.
eSilicon -- Enabling Your Silicon Success™
eSilicon is a registered trademark, and the eSilicon logo and Enabling Your Silicon Success are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.
Contacts:
Sally Slemons
eSilicon Corporation
408.635.6409
Susan Cain
Cain Communications
408.393.4794
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Datum: 04.11.2014 - 13:00 Uhr
Sprache: Deutsch
News-ID 349386
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Town:
SAN JOSE, CA
Kategorie:
Electronic Components
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