Cycle-accurate trace boosts performance optimization capabilities of UltraSoC embedded analytics infrastructure
Designers of SSDs, servers, real-time applications will benefit
(firmenpresse) - CAMBRIDGE, UK – 7 May 2019 UltraSoC today announced new technology within its embedded monitoring and analytics infrastructure that allows designers of high-performance computing, storage and real-time devices to squeeze ultimate levels of performance from their products. The addition of cycle-accurate trace enables developers of real-time applications using UltraSoC’s embedded analytics to see not only what is happening inside devices, but critically, when something occurred.
Cycle-accurate tracing is increasingly important in real-time and performance-critical applications, where engineers need to optimize the operation of their hardware and software code down to the level of single clock cycles – the smallest unit of time recognized by a CPU, GPU, DSP or accelerator. Cycle accurate tracing will initially be available as part of UltraSoC’s processor trace solution for RISC-V, the rapidly-growing open source processor initiative.
“Squeezing the last available drop of performance is increasingly important, both for our customers in the semiconductor industry, and their customers, who are creating end products like disk drives, automobiles and server platforms, using the SoCs we enable,” said Gajinder Panesar, CTO at UltraSoC. “In a world where ‘every cycle counts’, we’re helping to facilitate faster data access, better compute performance and optimal efficiency.”
Because UltraSoC’s analytics and monitoring technology is embedded directly in the chip’s hardware, it can capture events within an SoC that occur much more quickly – typically in the space of nanoseconds – than is possible using other techniques. Access to this cycle-accurate trace information means customers working on deeply embedded applications will be able to see exactly how many cycles their code is taking to execute, whether there are stalls and dependencies, and for how long they last. Armed with this information, designers of these critical systems can make further optimizations and achieve maximum efficiency gains.
The new cycle accurate trace capabilities build on UltraSoC’s leadership in RISC-V development and debug. In early 2018, the company announced the industry’s first and still the only commercial trace encoder IP designed for RISC-V, providing a mechanism to monitor the program execution of a CPU in real time. It encodes instruction execution and, optionally, data memory accesses, and outputs a highly compressed trace format. External software can later take this data and use it to reconstruct the program execution flow. UltraSoC’s RISC-V Trace Encoder is developed to be compliant with RISC-V standards, while offering a number of powerful features such as data and instruction tracing, a range of counters and timers and a fast profiling facility, clearly differentiating it from open source alternatives which implement the baseline RISC-V standard requirements.
Software does not always behave as expected due to interaction with other cores’ software, peripherals, realtime events, poor implementation or some combination of all of the above; the result is that real-time behavior is affected. Processor trace is a key requirement for system developers because it allows the behavior of a program to be viewed in detail, instruction-by-instruction – cycle accurate trace allows you to see when it was executed. The UltraSoC RISC-V Trace Encoder supports 32 and 64-bit RISC-V designs and the IP block integrates smoothly with the rest of the UltraSoC portfolio, supporting open and industry standard architectures to put self-analytic capabilities at the heart of SoCs.
From this week, UltraSoC is participating in the RISC-V China Roadshow - a series of free events to help get started with RISC-V designs. The events are taking place in Shenzhen on 6th May; Chengdu on 8th May; Shanghai on 13th May; Hangzhou on 14th May; Beijing on 16th May.
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Datum: 07.05.2019 - 14:32 Uhr
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News-ID 592130
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